This invention relates generally to resistive random-access memory cells.
Resistive random-access memory (RRAM) is a non-volatile memory technology in which the fundamental storage unit (the “cell”) includes a RRAM material located between a pair of electrodes. The RRAM material in these cells is an electrically-insulating matrix which normally presents a high resistance to electric current. However, due to properties of the RRAM matrix or of the combination of matrix and electrode materials, it is a particular property of RRAM cells that an electrically-conductive path can be formed within the high-resistance matrix by application of a suitable voltage to the electrodes. This conductive path extends though the matrix in a direction between the electrodes.
When the path connects the two electrodes the resistance of the memory cell drops dramatically, leaving the cell in a low-resistance “SET” state. The conductive path can be broken or eliminated by application of another “RESET” voltage to the electrodes, returning the cell to the high-resistance RESET state. Hence by appropriate application of SET and RESET pulses in a data write operation, individual cells can be programmed into one of two states with measurably-different resistance values permitting storage of information with 1-bit per cell. The programmed cell state can be determined in a read operation using cell resistance as a metric for cell state. On application of a read voltage to the electrodes, the current which flows through the cell depends on the cell's resistance, whereby cell current can be measured to determine the cell state. The read voltage is significantly lower than the write voltage used for programming so that the read operation does not disturb the programmed cell state.
The conductive path can be formed by a number of different mechanisms in RRAM cells. This is illustrated schematically in FIGS. 1a to 1c of the accompanying drawings for different RRAM cell-types. FIG. 1a illustrates migration of metal ions from an active electrode (silver) towards an inactive electrode (platinum) through a high-resistance ion conducting layer providing the insulating matrix between the electrodes. The resulting metal filament provides the conductive path in this type of conductive-bridge RRAM cell. FIG. 1b illustrates conductive path formation in oxide RRAM and metal-oxide RRAM cells. Here the path is formed by oxygen vacancies or metal precipitates, respectively, resulting from migration of oxygen ions in the insulating matrix. FIG. 1c illustrates conductive path formation by graphene (sp2) clusters in an amorphous carbon matrix disposed between top and bottom electrodes (e.g. of copper and titanium nitride, respectively) of a carbon RRAM cell.
In each case, the cell resistance decreases with increasing length of the conductive path across the insulating matrix. In general, the path “length” as used herein refers to effective path length corresponding to a particular configuration of the conductive path in the matrix. The nature of this conductive path as well as its configuration can vary across the variety of physical mechanisms exploited for path formation in RRAM devices, but different configurations equate to a different effective length of the conductive path. The path “length” as used herein can therefore correspond to an aggregate length if the path is fragmented, rather than continuous, and thus formed by two or more disconnected portions. Depending on cell-type, the RESET cell state can correspond to complete dissociation of the path-forming mechanisms, eliminating the path entirely, or only partial dissociation resulting in a gap or discontinuity in the path.
There are a number of problems associated with conventional RRAM technology. Switching between the SET and RESET states provides effective operation for two-state (or so-called “single-level”) RRAM cells. However, realization of “multi-level” RRAM cells (i.e. cells with s>2 programmable states) is challenging. Multilevel operation requires use of two or more “high-resistance” programmed states in which the conductive path has different lengths but does not fully bridge the RRAM matrix. Two such states are illustrated schematically in FIG. 2 of the accompanying drawings. There is a difference of several orders of magnitude in the resistivities of the conductive path and the insulating matrix. As a consequence, it is difficult to distinguish between such different high-resistance states using standard sensing schemes because sensing very high resistance values is difficult at high bandwidth. In addition, the transport properties of RRAM cells are complex and not yet fully understood, so it is difficult to predict the operating characteristics with the accuracy necessary for reliable multilevel operation. Moreover, the resistance of the RRAM matrix material is subject to variability from cell to cell and subject to effects such as low-frequency noise and drift. Resistance drift causes the resistance of the insulating matrix of a given cell to increase in value over time. These effects cause the read measurements for high-resistance cell states to vary with time in a stochastic manner further complicating the task of cell-state detection on readback.
Another problem is that the RESET current is still prohibitively large in many RRAM technologies. The RESET current can be reduced by reducing the volume or increasing the resistivity of the insulating matrix. However, these measures compound the problem discussed above by increasing the resistance of the high-resistance cell states. It is then even more difficult to sense resistance values for these states with a reasonable sensing bandwidth. Another potential problem is so-called “thermal disturb.” As dimensions are reduced for low technology nodes, heat generated during writing to one RRAM cell can disturb the programmed state in an adjacent memory cell.
A further problem is the occurrence of “sneak-path currents.” These undesirable current paths can occur in passive cross-bar memory array architectures when cells in the SET state create a low-resistance current path during reading of a neighboring cell, causing connections between adjacent bit-lines or word-lines. This can make reading of the addressed cell difficult, leading to a wrong interpretation of the stored bit. To avoid this problem, an access device, such as a transistor, can be connected to each cell at the expense of increased circuit complexity and reduced storage density. An alternative approach, based on a “complementary resistive switch,” is proposed in “Complementary resistive switches for passive nanocrossbar memories,” Linn et al., Nature Materials, May 2010. Two bipolar cell elements A and B are connected antiserially into one complementary resistive switch (CRS) cell. The proposed cell has two programmable states, both being high-resistance state, corresponding to element A being in the low-resistance state and element B being in a high-resistance state and vice versa. Cell-state can be detected by determining whether the cell switches to a low-resistance ON state (high current) or remains in the high-resistance state (low current) on application of a read voltage. More recently, this 2-RRAM stack CRS cell concept was shown to work in single-stack bipolar RRAM devices (“Complementary switching in metal oxides: toward diode-less crossbar RRAMs,” Nardi et al. IEDM 2011).
This single-stack cell has two high-resistance programmable states corresponding to the asymmetric RESET states obtained by applying different-polarity RESET pulses to the cell. In the first state, the conductive path has a longer portion near the one electrode than the other. This configuration is reversed in the other state so that the high-resistance “gap” in the conductive path is closer to a different electrode in each state. Cell-state can be detected by determining whether the cell switches to a low-resistance SET state on sweeping the voltage towards a positive or a negative polarity. While these complementary cell techniques avoid sneak-path currents, the read operation necessarily destroys the programmed cell state, requiring re-programming after reading.
Improved RRAM cells are desired.